// matlab
// OpenTF/main/Code/mac/model/matlab/systolic_array

`include  "define.sv"

module tb(/*AUTOARG*/
   // Outputs
   w_post_code, tx_en, tx_data,
   // Inputs
   rx_vld, rx_err, rx_data
   );

parameter  UART_ADDR = 16'h03f8 ;
parameter  LED_ADDR  = 16'h0080 ;

parameter  UART_FIFO_DEPTH =  8            ;
parameter  UART_FIFO_MAX   = (1<<UART_FIFO_DEPTH) -2  ;

parameter  UART_IDLE_STATE  = 2'd0 ;
parameter  UART_WFIFO_STATE = 2'd1 ;
parameter  LED_STATE        = 2'd2 ;


////////////////////////////////////////////////////////////////////////////


///////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////////////



  /*AUTOINPUT*/
  // Beginning of automatic inputs (from unused autoinst inputs)
  input [7:0]		rx_data;		// To u_spi2uart of spi2uart.v
  input			rx_err;			// To u_spi2uart of spi2uart.v
  input			rx_vld;			// To u_spi2uart of spi2uart.v
  // End of automatics
  /*AUTOOUTPUT*/
  // Beginning of automatic outputs (from unused autoinst outputs)
  output [7:0]		tx_data;		// From u_spi2uart of spi2uart.v, ...
  output		tx_en;			// From u_spi2uart of spi2uart.v, ...
  output [7:0]		w_post_code;		// From u_spi2uart of spi2uart.v, ...
  // End of automatics
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire [2:0]		addr_valid;		// From driver of driver.v
  wire [63:0]		address;		// From driver of driver.v
  wire			clk;			// From u_clk_gen of clk_gen.v
  wire [7:0]		command;		// From driver of driver.v
  wire			command_valid;		// From driver of driver.v
  wire [7:0]		cycle;			// From driver of driver.v
  wire [7:0]		data_from_ip;		// From driver of driver.v
  wire			data_req;		// From driver of driver.v
  wire			data_valid;		// From driver of driver.v
  wire [15:0]		error_data;		// From driver of driver.v
  wire			error_en;		// From driver of driver.v
  wire			hdr_valid;		// From driver of driver.v
  wire [11:0]		length;			// From driver of driver.v
  wire [7:0]		message_code;		// From driver of driver.v
  wire [31:0]		message_specific;	// From driver of driver.v
  wire			message_valid;		// From driver of driver.v
  wire			rst;			// From u_rst_gen of rst_gen.v
  wire [3:0]		tag;			// From driver of driver.v
  wire			tx_rdy;			// From driver of driver.v
  // End of automatics



/* rst_gen AUTO_TEMPLATE (
  .rst_p(rst),
  .rst_n(),             
 );
*/

  /* axi_ram  AUTO_TEMPLATE "\([0-9]+\)"  (
	.s_axi_\(.*\) 		(m@_axi_\1[]),
 );
*/

spi2uart #(
  /*AUTOINSTPARAM*/
	   // Parameters
	   .UART_ADDR			(UART_ADDR),
	   .LED_ADDR			(LED_ADDR),
	   .UART_FIFO_DEPTH		(UART_FIFO_DEPTH),
	   .UART_FIFO_MAX		(UART_FIFO_MAX),
	   .UART_IDLE_STATE		(UART_IDLE_STATE),
	   .UART_WFIFO_STATE		(UART_WFIFO_STATE),
	   .LED_STATE			(LED_STATE))u_spi2uart(
							/*AUTOINST*/
							       // Outputs
							       .tx_en		(tx_en),
							       .tx_data		(tx_data[7:0]),
							       .w_post_code	(w_post_code[7:0]),
							       // Inputs
							       .clk		(clk),
							       .rst		(rst),
							       .tx_rdy		(tx_rdy),
							       .rx_vld		(rx_vld),
							       .rx_data		(rx_data[7:0]),
							       .rx_err		(rx_err),
							       .command_valid	(command_valid),
							       .command		(command[7:0]),
							       .error_en	(error_en),
							       .error_data	(error_data[15:0]),
							       .data_req	(data_req),
							       .data_valid	(data_valid),
							       .data_from_ip	(data_from_ip[7:0]),
							       .addr_valid	(addr_valid[2:0]),
							       .address		(address[63:0]),
							       .hdr_valid	(hdr_valid),
							       .cycle		(cycle[7:0]),
							       .tag		(tag[3:0]),
							       .length		(length[11:0]),
							       .message_valid	(message_valid),
							       .message_code	(message_code[7:0]),
							       .message_specific(message_specific[31:0]));
 



  clk_gen u_clk_gen (
             /*AUTOINST*/
		     // Outputs
		     .clk		(clk));

  rst_gen u_rst_gen (
            /*AUTOINST*/
		     // Outputs
		     .rst_n		(),			 // Templated
		     .rst_p		(rst));			 // Templated

driver #( 
/*AUTOINSTPARAM*/
	 // Parameters
	 .UART_ADDR			(UART_ADDR),
	 .LED_ADDR			(LED_ADDR))  driver(
            /*AUTOINST*/
							    // Outputs
							    .tx_rdy		(tx_rdy),
							    .command_valid	(command_valid),
							    .command		(command[7:0]),
							    .error_en		(error_en),
							    .error_data		(error_data[15:0]),
							    .data_req		(data_req),
							    .data_valid		(data_valid),
							    .data_from_ip	(data_from_ip[7:0]),
							    .addr_valid		(addr_valid[2:0]),
							    .address		(address[63:0]),
							    .hdr_valid		(hdr_valid),
							    .cycle		(cycle[7:0]),
							    .tag		(tag[3:0]),
							    .length		(length[11:0]),
							    .message_valid	(message_valid),
							    .message_code	(message_code[7:0]),
							    .message_specific	(message_specific[31:0]),
							    // Inputs
							    .clk		(clk),
							    .rst		(rst));


monitor u_monitor(/*AUTOINST*/
		  // Outputs
		  .tx_en		(tx_en),
		  .tx_data		(tx_data[7:0]),
		  .w_post_code		(w_post_code[7:0]));



  dump dump ();




endmodule

// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-library-directories:("."  "../src/"   )
// End:
